2020/07/19 by Mahmood Azhar Qureshi, Qureshi, Mahmood Azhar, Arslan Munir +1
Computer Science · Engineering · Neuroscience · #Advanced Malware Detection Techniques #Advanced Memory and Neural Computing #Cryptography and Security (cs.CR) #FOS: Computer and information sciences #Neuroscience and Neural Engineering #Physical Unclonable Functions (PUFs) and Hardware Security
paper · pdf · doi:10.48550/arxiv.2007.09588
openalex publication_date 2020/07/19 · openalex created_date 2022/07/26 · openalex updated_date 2026/07/28
Physically unclonable functions (PUFs) can be employed for device\nidentification, authentication, secret key storage, and other security tasks.\nHowever, PUFs are susceptible to modeling attacks if a number of PUFs'\nchallenge-response pairs (CRPs) are exposed to the adversary. Furthermore, many\nof the embedded devices requiring authentication have stringent resource\nconstraints and thus require a lightweight authentication mechanism. We propose\nPUF-RLA, a PUF-based lightweight, highly reliable authentication scheme\nemploying binary string shuffling. The proposed scheme enhances the reliability\nof PUF as well as alleviates the resource constraints by employing error\ncorrection in the server instead of the device without compromising the\nsecurity. The proposed PUF-RLA is robust against brute force, replay, and\nmodeling attacks. In PUF-RLA, we introduce an inexpensive yet secure stream\nauthentication scheme inside the device which authenticates the server before\nthe underlying PUF can be invoked. This prevents an adversary from brute\nforcing the device's PUF to acquire CRPs essentially locking out the device\nfrom unauthorized model generation. Additionally, we also introduce a\nlightweight CRP obfuscation mechanism involving XOR and shuffle operations.\nResults and security analysis verify that the PUF-RLA is secure against brute\nforce, replay, and modeling attacks, and provides ~99% reliable authentication.\nIn addition, PUF-RLA provides a reduction of 63% and 74% for look-up tables\n(LUTs) and register count, respectively, in FPGA compared to a recently\nproposed approach while providing additional authentication advantages.\n