2018/01/12 by Vinh Ngo, Arnau Casadevall, Ngo, Vinh +8
Computer Science · Engineering · #Advanced Neural Network Applications #Algorithm #Architecture #Artificial intelligence #Autonomous Vehicle Technology and Safety #Computer Vision and Pattern Recognition (cs.CV) #Computer hardware #Computer science #Embedded system #Engineering #Extractor #FOS: Computer and information sciences #Feature (linguistics) #Field-programmable gate array #Implementation #Key (lock) #Operating system #Pedestrian #Pedestrian detection #Power (physics) #Power consumption #Real-time computing #State (computer science) #Support vector machine #Throughput #Video Surveillance and Tracking Methods #cs.CV
paper · pdf · doi:10.48550/arxiv.1802.02187
Presented at HIP3ES, 2018
arxiv created 2018/01/12 · openalex publication_date 2018/01/12 · arxiv updated 2018/02/08 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/04
Pedestrian detection is one of the key problems in emerging self-driving car industry. And HOG algorithm has proven to provide good accuracy for pedestrian detection. There are plenty of research works have been done in accelerating HOG algorithm on FPGA because of its low-power and high-throughput characteristics. In this paper, we present a high-performance HOG architecture for pedestrian detection on a low-cost FPGA platform. It achieves a maximum throughput of 526 FPS with 640x480 input images, which is 3.25 times faster than the state of the art design. The accelerator is integrated with SVM-based prediction in realizing a pedestrian detection system. And the power consumption of the whole system is comparable with the best existing implementations.