2019/10/10 by Gourav Datta, Haolin Cong, Datta, Gourav +5
Computer Science · Engineering · #Applied Physics (physics.app-ph) #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #FOS: Physical sciences #Interconnection Networks and Systems #Low-power high-performance VLSI design #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.1910.04907
openalex publication_date 2019/10/10 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.