Pipelined Parallel FFT Architecture

2017/07/06 by Tanaji Umaji Kamble, Kamble, Tanaji U., Basavarja Patil +3
Computer Science · #Digital Filter Design and Implementation #FOS: Computer and information sciences #FOS: Mathematics #Hardware Architecture (cs.AR) #Image and Signal Denoising Methods #Numerical Methods and Algorithms #Optimization and Control (math.OC)

paper · pdf · doi:10.48550/arxiv.1707.01697

openalex publication_date 2017/07/06 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

In this paper, an optimized efficient VLSI architecture of a pipeline Fast Fourier transform (FFT) processor capable of producing the reverse output order sequence is presented. Paper presents Radix-2 multipath delay architecture for FFT calculation. The implementation of FFT in hardware is very critical because for calculation of FFT number of butterfly operations i.e. number of multipliers requires due to which hardware gets increased means indirectly cost of hardware is automatically gets increased. Also multiplier operations are slow that's why it limits the speed of operation of architecture. The optimized VLSI implementation of FFT algorithm is presented in this paper. Here architecture is pipelined to optimize it and to increase the speed of operation. Also to increase the speed of operation 2 levels parallel processing is used.

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