2017/11/21 by Igor C. Silva, Silva, Igor C., Gabriel H. A. Silva +5
Engineering · #FOS: Electrical engineering #Signal Processing (eess.SP) #eess.SP #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.1711.07757
DINCON 2017 - Conferencia Brasileira de Dinamica, Controle e Aplicacoes - Sao Jose do Rio Preto - Brazil. 7 pages. In Portuguese
arxiv created 2017/11/21 · arxiv updated 2017/11/22
This paper proposes a model validation method that incorporates error due to numerical procedures. Two identified models for Sine Map and Duffing-Ueda Circuit systems have been investigated. The indexes RMSE and MAPE have been applied. We have shown that after some few iterates, it is possible to notice some significative difference between index provided in the literature. This difference has been computed in around 34%.