Y. Hoshino

1. A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay
   1996/11/01 by T. Saeki, Y. Nakaoka, Masafumi Fujita +43 · 2 citations
   Engineering · Computer Science · #Low-power high-performance VLSI design #Parallel Computing and Optimization Techniques #Semiconductor materials and devices